Method of making truncated power enhanced drift lateral DMOS...

Details Method of making truncated power enhanced drift lateral DMOS... Method of making truncated power enhanced drift lateral DMOS...

2006-06-13

2006-06-13

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S270000, C257S335000

Reexamination Certificate

active

07060545

ABSTRACT:
A method and system for providing a power enhanced lateral DMOS device is disclosed. The method and system comprise providing a semiconductor substrate with a plurality of source/body structures thereon. The method and system further comprise providing a slot in the semiconductor substrate between the plurality of source/body structures to provide a truncated source; and providing a metal within the slot to provide a ground strap device.

REFERENCES:
patent: 5719411 (1998-02-01), Ajit
patent: 5767546 (1998-06-01), Williams et al.
patent: 6525372 (2003-02-01), Baliga

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