Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Reexamination Certificate
2006-11-14
2006-11-14
Smith, Matthew (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
C257S707000
Reexamination Certificate
active
07135781
ABSTRACT:
Disclosed is a semiconductor device that includes an electrically insulating, sheet-like substrate (301) with first and second surfaces (301a, 301b), at least one opening (310), and a certain thickness (302). On the first surface are a plurality of electrically conductive routing strips and a plurality of contact pads (330); at least one of the contact pads is electrically connected with at least one of the routing strips, and may have a solder body (901) attached. A semiconductor chip (102) is positioned in the opening while leaving a gap (311) to the substrate; the chip has an active surface (102a) including at least one bond pad (103), and a passive surface (102b) substantially coplanar with the second substrate surface (301b). Substrate thickness and chip thickness may be substantially equal. Bonding elements (501) bridge the gap to connect electrically bond pad and routing strip. Encapsulation material (701) protects the active chip surface and the bonding elements, and fills the gap so that the filler surface (701a) is substantially coplanar with the passive chip surface and the second substrate surface. The support tape (101) used in assembly is discarded.
REFERENCES:
patent: 5072283 (1991-12-01), Bolger
patent: 5519936 (1996-05-01), Andros et al.
patent: 5736785 (1998-04-01), Chiang et al.
patent: 6057601 (2000-05-01), Lau et al.
patent: 6215195 (2001-04-01), Koduri
patent: 6294100 (2001-09-01), Fan et al.
patent: 6483187 (2002-11-01), Chao et al.
patent: 6585905 (2003-07-01), Fan et al.
patent: 6815836 (2004-11-01), Ano
patent: 2003/0230801 (2003-12-01), Jiang et al.
patent: 2004/0191954 (2004-09-01), Ano
patent: 2005/0156322 (2005-07-01), Smith et al.
Kalidas Navinchandra
Libres Jeremias P.
Pierce Michael P.
Brady III Wade James
Malsawma Lex H.
Smith Matthew
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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