Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-06-27
2006-06-27
Ho, Tu-Tu (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S324000, C257S369000, C257S411000
Reexamination Certificate
active
07067369
ABSTRACT:
A flash memory cell transistor and a method for fabricating the same compensates a work function difference of a pMOS and a nMOS with a triple gate insualting film by using electron density trapped in a pMOS gate insulating film. The flash memory cell transistor comprises a p-well region and a n-well region. The nMOS region comprises a nMOS channel ion-implantation region on the p-well region, a second gate oxide film on the nMOS channel ion-implantation region and a first n+ polysilicon gate electrode on the second gate oxide film. The pMOS region comprises a pMOS channel ion-implantation region on the n-well region, a first gate oxide film, an insulating film having an electron trap and the second gate oxide film which are sequentially formed on the pMOS channel ion-implantation region, and a second n+ polysilicon gate electrode on the second gate oxide film.
REFERENCES:
patent: 2004/0180501 (2004-09-01), Liu
Tomoko Ogura et al., “Embedded Twin MONOS Flash Memories with 4ns and 15ns Fast Access Times”, Symposium on VLSI Circuits Digest of Technical Papers, 2003, pp. 207-210.
Heller Ehrman LLP
Ho Tu-Tu
Hynix / Semiconductor Inc.
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