Methods of testing interconnect lines in programmable logic...

Details Methods of testing interconnect lines in programmable logic... Methods of testing interconnect lines in programmable logic...

2006-10-17

2006-10-17

Moise, Emmanuel L. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C326S038000

Reexamination Certificate

active

07124338

ABSTRACT:
Methods and systems for testing PLD interconnect lines, e.g., interconnect lines driven by a plurality of programmable buffers. Each programmable buffer has an associated memory element. The memory elements are configured to form a shift register, with one of the buffers and the interconnect line inserted between two of the memory elements. The signal path through the shift register is tested using a first test pattern. Partial reconfiguration is then used to change the insertion point of the interconnect line in the signal path by changing the configuration of the interconnect structure and using a second one of the buffers. A second test pattern is then used to test the second buffer. This sequence is repeated until each of the buffers has been tested. Because only small changes are required, the partial reconfiguration requires loading only small amounts of configuration data, significantly reducing test time compared to presently-known test methods.

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Xilinx, Inc.; XAPP290 v1.0 Application Note; “Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations”; published May 17, 2002; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; 23 pages.

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