MIS semiconductor device and manufacturing method thereof

Details MIS semiconductor device and manufacturing method thereof MIS semiconductor device and manufacturing method thereof

2006-02-21

2006-02-21

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S306000, C438S307000, C438S595000

Reexamination Certificate

active

07001818

ABSTRACT:
By suppressing a short-channel effect of a MIS field-effect transistor and reducing a fringing capacitance of a gate, a signal delay in the transistor can be shortened. The MIS field-effect transistor is formed d by forming a side-wall spacer from a dielectric having a large dielectric constant and then forming an impurity diffusion layer area with the side-wall spacer used as an introduction end in an ion implantation process to introduce impurities. In this case, the side wall of the side-wall spacer having the large dielectric constant has an optimum film thickness in the range from 5 nm to 15 nm, which is required for achieving a large driving current. On the other hand, a side-wall spacer on an outer side is made of a silicon-dioxide film, which is a dielectric having a small dielectric constant.

REFERENCES:
patent: 5234850 (1993-08-01), Liao
patent: 5824588 (1998-10-01), Liu
patent: 6043545 (2000-03-01), Tseng et al.
patent: 6344677 (2002-02-01), Higuchi
patent: 6399451 (2002-06-01), Lim et al.
patent: 6448167 (2002-09-01), Wang et al.
patent: 6661067 (2003-12-01), Ngo et al.
patent: 5-3206 (1993-01-01), None
patent: 7-245391 (1995-09-01), None

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