Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-02-28
2006-02-28
Flynn, Nathan J. (Department: 2826)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S201000, C438S260000
Reexamination Certificate
active
07005338
ABSTRACT:
A floating gate (110) of a nonvolatile memory cell is formed in a trench (114) in a semiconductor substrate (220). A dielectric (128) covers the surface of the trench. The wordline (140) has a portion overlying the trench. The cell's floating gate transistor has a first source/drain region (226), a channel region (224), and a second source/drain region (130). The dielectric (128) is stronger against leakage near at least a portion of the first source/drain region (122) than near at least a portion of the channel region. The stronger portion (128.1) of the additional dielectric improves data retention without increasing the programming and erase times if the programming and erase operations do not rely on a current through the stronger portion. Additional dielectric (210) has a portion located below the top surface of the substrate between the trench and a top part of the second source/drain region (130). The second source/drain region has a part located below the additional dielectric and meeting the trench. The additional dielectric can be formed with shallow trench isolation technology. The additional dielectric reduces the capacitance between the second source/drain region (130) and the floating gate.
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Chan Vei-Han
Ding Yi
Flynn Nathan J.
MacPherson Kwok & Chen & Heid LLP
ProMOS Technologies Inc.
Sefer Ahmed N.
Shenker Michael
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