Fabrication of dielectric for a nonvolatile memory cell...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S264000, C438S266000, C438S593000

Reexamination Certificate

active

07060565

ABSTRACT:
A memory cell (110) has a select gate (140) and at least two floating gates (160). A gate dielectric (150) for the floating gates (160) is formed by thermal oxidation simultaneously with as a dielectric on a surface of the select gate (140). The dielectric thickness on the select gate is controlled by the dopant concentration in the select gate. Other features are also provided.

REFERENCES:
patent: 4701776 (1987-10-01), Perlegos et al.
patent: 5402371 (1995-03-01), Ono
patent: 5408115 (1995-04-01), Chang
patent: 5424979 (1995-06-01), Morii
patent: 5445983 (1995-08-01), Hong
patent: 5633185 (1997-05-01), Yiu et al.
patent: 5668757 (1997-09-01), Jeng
patent: 5705415 (1998-01-01), Orlowski et al.
patent: 5821143 (1998-10-01), Kim et al.
patent: 5856943 (1999-01-01), Jeng
patent: 5901084 (1999-05-01), Ohnakado
patent: 5910912 (1999-06-01), Hsu et al.
patent: 5912843 (1999-06-01), Jeng
patent: 5918124 (1999-06-01), Sung
patent: 6011725 (2000-01-01), Eitan
patent: 6040216 (2000-03-01), Sung
patent: 6057575 (2000-05-01), Jenq
patent: 6107141 (2000-08-01), Hsu et al.
patent: 6130129 (2000-10-01), Chen
patent: 6133098 (2000-10-01), Ogura et al.
patent: 6134144 (2000-10-01), Lin et al.
patent: 6162682 (2000-12-01), Kleine
patent: 6171909 (2001-01-01), Ding et al.
patent: 6187636 (2001-02-01), Jeong
patent: 6200856 (2001-03-01), Chen
patent: 6207507 (2001-03-01), Wang
patent: 6214669 (2001-04-01), Hisamune
patent: 6218689 (2001-04-01), Chang et al.
patent: 6228695 (2001-05-01), Hsieh et al.
patent: 6232185 (2001-05-01), Wang
patent: 6261903 (2001-07-01), Chang et al.
patent: 6265739 (2001-07-01), Yaegashi et al.
patent: 6266278 (2001-07-01), Harari et al.
patent: 6291297 (2001-09-01), Chen
patent: 6326661 (2001-12-01), Dormans et al.
patent: 6344993 (2002-02-01), Harari et al.
patent: 6355524 (2002-03-01), Tuan et al.
patent: 6365457 (2002-04-01), Choi
patent: 6388293 (2002-05-01), Ogura et al.
patent: 6414872 (2002-07-01), Bergemont et al.
patent: 6420231 (2002-07-01), Harari et al.
patent: 6436764 (2002-08-01), Hsieh
patent: 6437360 (2002-08-01), Cho et al.
patent: 6438036 (2002-08-01), Seki et al.
patent: 6468865 (2002-10-01), Yang et al.
patent: 6486023 (2002-11-01), Nagata
patent: 6518618 (2003-02-01), Fazio et al.
patent: 6541324 (2003-04-01), Wang
patent: 6541829 (2003-04-01), Nishinohara et al.
patent: 6566196 (2003-05-01), Haselden et al.
patent: 6635533 (2003-10-01), Chang et al.
patent: 6642103 (2003-11-01), Wils et al.
patent: 6660589 (2003-12-01), Park
patent: 6696340 (2004-02-01), Furuhata
patent: 6747310 (2004-06-01), Fan et al.
patent: 6764905 (2004-07-01), Jeng et al.
patent: 6803276 (2004-10-01), Kim et al.
patent: 2002/0064071 (2002-05-01), Takahashi et al.
patent: 2002/0197888 (2002-12-01), Huang et al.
patent: 2003/0205776 (2003-11-01), Yaegashi et al.
patent: 2003/0218908 (2003-11-01), Park et al.
patent: 2004/0004863 (2004-01-01), Wang
patent: 0 938 098 (1999-08-01), None
U.S. Appl. No. 10/798,475, entitled “Fabrication of Conductive Lines Interconnecting Conductive Gates in Nonvolatile Memories and Non-Volatile Memory Structures,” Filed on Mar. 10, 2004.
U.S. Appl. No. 10/797,972, entitled “Fabrication of Conductive Lines Interconnecting First Conductive Gates in Nonvolatile Memories Having Second Conductive Gates Provided By Conductive Gates Lines, Wherein The Adjacent Conductive Gate Lines For The Adjacent Columns Are Spaced From Each Other, And Non-Volatile Memory Structures,” Filed on Mar. 10, 2004.
U.S. Appl. No. 10/440,466, entitled “Fabrication Of Conductive Gates For Nonvolatile Memories From Layers With Protruding Portions,” Filed on May 16, 2003.
U.S. Appl. No. 10/440,005, entitled “Fabrication of Dielectric On A Gate Surface To Insulate The Gate From Another Element Of An Integrated Circuit,” Filed on May 16, 2003.
U.S. Appl. No. 10/440,508, entitled “Fabrication Of Gate Dielectric In Nonvolatile Memories Having Select, Floating And Control Gates,” Filed on May 16, 2003.
U.S. Appl. No. 10/440,500, entitled “Integrated Circuits With Openings that Allow Electrical Contact To Conductive Features Having Self-Aligned Edges,” Filed on May 16, 2003.
U.S. Appl. No. 10/393,212, entitled “Nonvolatile Memories And Methods Of Fabrication,” Filed on Mar. 19, 2003.
U.S. Appl. No. 10/411,813, entitled “Nonvolatile Memories With A Floating Gate Having An Upward Protrusion,” Filed on Apr. 10, 2003.
U.S. Appl. No. 10/393,202, entitled “Fabrication of Integrated Circuit Elements In Structures With Protruding Features,” Filed on Mar. 19, 2003.
U.S. Appl. No. 10/631,941, entitled “Nonvolatile Memory Cell With Multiple Floating Gates Formed After The Select Gate,” Filed on Jul. 30, 2003.
U.S. Appl. No. 10/632,155, entitled “Nonvolatile Memory Cells With Buried Channel Transistors,” Filed on Jul. 30, 2003.
U.S. Appl. No. 10/632,007, entitled “Arrays Of Nonvolatile Memory Cells Wherin Each Cell Has Two Conductive Floating Gates,” Filed on Jul. 30, 2003.
U.S. Appl. No. 10/632,154, entitled “Fabrication Of Gate Dielectric In Nonvolatile Memories In Which A Memory Cell Has Mutiple Floating Gates,” Filed on Jul. 30, 2003.
U.S. Appl. No. 10/631,552, entitled “Nonvolatile Memories And Methods Of Fabrication,” Filed on Jul. 30, 2003.
U.S. Appl. No. 10/632,186, entitled “Nonvolatile Memory Cell With Multiple Floating Gates Formed After The Select Gate And Having Upward Protrusions,” Filed on Jul. 30, 2003.
Shirota, Riichiro “A Review of 256Mbit NAND Flash Memories and NAND Flash Future Trend,” Feb. 2000, Nonvolatile Memory Workshop in Monterey, California, pp. 22-31.
Naruke, K.; Yamada, S.; Obi, E.; Taguchi, S.; and Wada, M. “A New Flash-Erase EEPROM Cell With A Sidewall Select-Gate On Its Source Side,” 1989 IEEE, pp. 604-606.
Wu, A.T.; Chan T.Y.; Ko, P.K.; and Hu, C. “A Novel High-Speed, 5-Volt Programming EPROM Structure With Source-Side Injection,” 1986 IEEE, 584-587.
Mizutani, Yoshihisa; and Makita, Koji “A New EPROM Cell With A Sidewall Floating Gate Fro High-Density and High Performance Device,” 1985 IEEE, 635-638.
Ma, Y.; Pang, C.S.; Pathak, J.; Tsao, S.C.; Chang, C.F.; Yamauchi, Y.; Yoshimi, M. “A Novel High Density Contactless Flash Memory Array Using Split-Gate Source-Side-Injection Cell for 5V-Only Applications,” 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 49-50.
Mih, Rebecca et al. “0.18um Modular Triple Self-Aligned Embedded Split-Gate Flash Memory,” 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 120-121.
Ma, Yale et al., “A Dual-Bit Split-Gate EEPROM (DSG) Cell in Contactless Array for Single Vcc High Density Flash Memories,” 1994 IEEE, 3.5.1-3.5.4.
Spinelli, Alessandro S., “Quantum-Mechanical 2D Simulation of Surface-and Buried-Channel p-MOS,”2000 International Conference on Simulation of Semiconductor Processes and Devices: SISPAD 2000, Seattle, WA Sep. 6-8, 2000.
Kim, K.S. et al. “A Novel Dual String NOR (DuSnor) Memory Cell Technology Scalable to the 256 Mbit and 1 Gbit Flash Memories,” 1995 IEEE 11.1.1-11.1.4.
Bergemont, A. et al.“NOR Virtual Ground (NVG)- A New Scaling Concept for Very High Density FLAS EEPROM and its Implementation in a 0.5 um Process,” 1993 IEEE 2.2.1-2.2.4.
Van Duuren, Michiel et al., “Compact poly-CMP Embedded Flash Memory Cells For One or Two Bit Storage,” Philips Research Leuven, Kapeldreef75, B3001 Leuven, Belgium, pp. 73-74.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Fabrication of dielectric for a nonvolatile memory cell... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fabrication of dielectric for a nonvolatile memory cell..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication of dielectric for a nonvolatile memory cell... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3629670

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.