Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-02-28
2006-02-28
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S268000
Reexamination Certificate
active
07005346
ABSTRACT:
A memory cell has a vertical construction of a capacitor and a vertical FET arranged above the latter which can be produced with a lower outlay and in a technologically more reliable fashion. This is achieved by virtue of the fact that two first trenches running parallel and having a first depth are etched in the semiconductor substrate. Between the trenches is formed a web, which is connected to the semiconductor substrate at its narrow sides and which is severed at its underside and is separated from the semiconductor substrate. The suspended web is then provided with a closed dielectric. After a filling, the FET is applied and connected to the web as memory node.
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Dang Phuc T.
Infineon - Technologies AG
Slater & Matsil L.L.P.
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