Semiconductor chip packages and methods for fabricating the...

Details Semiconductor chip packages and methods for fabricating the... Semiconductor chip packages and methods for fabricating the...

2006-10-10

2006-10-10

Geyer, Scott B. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000

Reexamination Certificate

active

07119001

ABSTRACT:
Semiconductor chip packages of a wafer level and method for fabricating the same are disclosed, in which a wafer electrode pad is connected with an external circuit by a via-electrode penetrating a silicon wafer. An illustrated example package includes a wafer having a first surface and a second surface opposite the first surface; a semiconductor device having at least one of electrode pad on the first surface; a protective layer covering the first surface of the silicon wafer; a via-hole from the second surface to the electrode pad on the first surface, a via electrode within the via-hole; and a solder ball or a solder bump on the second surface for electrical connection between the via-electrode and an external circuit.

REFERENCES:
patent: 5851845 (1998-12-01), Wood et al.
patent: 6221769 (2001-04-01), Dhong et al.
patent: 2003-56174 (2003-07-01), None

Affiliated with

Also associated with

Rating

Semiconductor chip packages and methods for fabricating the... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor chip packages and methods for fabricating the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor chip packages and methods for fabricating the... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3624747