Method of fabricating dual voltage MOS transistors

Details Method of fabricating dual voltage MOS transistors Method of fabricating dual voltage MOS transistors

1998-06-30

2000-03-07

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438221, 438225, 438299, H01L 218234

Patent

active

060339586

ABSTRACT:
A method of forming dual voltage MOS transistors includes first forming a mask layer, covering one of the at least two device regions and exposing another one of the two device regions. A gate oxide layer is then formed by thermal oxidation on the exposed device region. After removing the mask layer and exposing another gate oxide formed therebeneath, polysilicon gates for both of the two device regions can be formed.

REFERENCES:
patent: 5432114 (1995-07-01), O
patent: 5502009 (1996-03-01), Lin
patent: 5506159 (1996-04-01), Enomoto
patent: 5716863 (1998-02-01), Arai
patent: 5888873 (1999-03-01), Krivokapic

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