Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-07-18
2006-07-18
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000, C714S724000
Reexamination Certificate
active
07080302
ABSTRACT:
The present invention provides a test system for a semiconductor device, the test system comprising: a test data generator for generating test data, the test data generator being provided in an output section; a delay circuit for, in order to use as expected-value data the test data after the test data is transferred through inside a chip, adjusting a time difference between the test data and the expected-value data; a comparator for, against the expected-value data, comparing and verifying the test data after the test data is transferred outside the chip, the comparator being provided in an input section; and an external wiring for connecting an output pin connected to the test data generator and an input pin connected to the comparator.
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Alphonse Fritz
Buchanan & Ingersoll PC
De'cady Albert
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