Method and apparatus for improving testability of I/O...

Details Method and apparatus for improving testability of I/O... Method and apparatus for improving testability of I/O...

2006-01-10

2006-01-10

Chung, Phung My (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S738000

Reexamination Certificate

active

06986087

ABSTRACT:
An embodiment of this invention provides a circuit and method for improving the testability of I/O driver/receivers. First, two separate I/O driver/receiver pads are electrically connected. A bit pattern generator in one of the I/O driver/receivers drives a bit pattern through a driver to the connected pads. The bit pattern is then driven through the receiver of a second I/O driver/receiver to a first clocked register. An identical bit pattern generator in the second I/O driver/receiver then drives an identical bit pattern into a second clocked register. A comparator compares the outputs of these two registers. If the two bit patterns don't match, the comparator signals there is a functional problem with one of the I/O driver/receivers.

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