Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-09-12
2006-09-12
Tran, Mai-Huong (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S003000, C438S240000, C438S653000
Reexamination Certificate
active
07105397
ABSTRACT:
According to the present invention, there is a provided a semiconductor device fabrication method having, forming a mask material in a surface portion of a semiconductor substrate, and forming a step having a projection by using the mask material; forming a dielectric film on the semiconductor substrate so as to fill the step and planarize an entire surface; annealing the dielectric film; etching back the dielectric film such that a surface of the dielectric film is positioned between upper and lower surfaces of the mask material; and removing the mask material to expose a surface of the projection of the semiconductor substrate.
REFERENCES:
patent: 6479405 (2002-11-01), Lee et al.
patent: 6706540 (2004-03-01), Hikosaka et al.
patent: 2003/0022522 (2003-01-01), Nishiyama et al.
patent: 2004/0072429 (2004-04-01), Hieda et al.
patent: 2000-114362 (2000-04-01), None
patent: 2000-183150 (2000-06-01), None
patent: 2001-308090 (2001-11-01), None
patent: 2002-203895 (2002-07-01), None
patent: 2002-367980 (2002-12-01), None
patent: 2003-31650 (2003-01-01), None
patent: WO 03/021636 (2003-03-01), None
Sato et al., “Advanced Spin Coating Film Transfer and Hot-Pressing Process for Global Planarization with Dielectric-Material-Viscosity Control,” Jpn. J. Appl. Phys. (Apr. 2002), 41:2367-73.
Jin-Hwa Heo et al., “Void Free and Low Stree Shallow Trench Isolation Technology using P-SOG for sub 0.1 μm Device”. Symposium On VLSI Technology Digest of Technical Papers. pp. 132-133 (2002).
Yukio Nishiyama et al., “Method for Manufacturing Semiconductor Device”, U.S. Appl. No. 10/193,143, filed Jul. 12, 2002.
Hieda Katsuhiko
Kiyotoshi Masahiro
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Tran Mai-Huong
LandOfFree
Semiconductor device and method of fabricating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method of fabricating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of fabricating the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3591376