Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-05-16
2006-05-16
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S221000, C438S223000, C257SE27064, C257SE21633, C257SE21642
Reexamination Certificate
active
07045410
ABSTRACT:
A method (200) of forming an isolation structure is disclosed, and includes forming a patterned isolation hard mask layer (206, 212) having an isolation opening associated therewith over a semiconductor body. An implant into the isolation opening is then performed (214), followed by forming an isolation trench (216) in the semiconductor body associated with the isolation opening. The isolation trench is then filled with a dielectric material (218).
REFERENCES:
patent: 4523369 (1985-06-01), Nagakubo
patent: 5719085 (1998-02-01), Moon et al.
patent: 5780353 (1998-07-01), Omid-Zohoor
patent: 5807789 (1998-09-01), Chen et al.
patent: 5863827 (1999-01-01), Joyner
patent: 5937309 (1999-08-01), Chuang
patent: 5956598 (1999-09-01), Huang et al.
patent: 5960276 (1999-09-01), Liaw et al.
patent: 6030882 (2000-02-01), Hong
patent: 6040232 (2000-03-01), Gau
patent: 6180490 (2001-01-01), Vassiliev et al.
patent: 6225187 (2001-05-01), Huang et al.
patent: 6245639 (2001-06-01), Tsai et al.
patent: 6492220 (2002-12-01), Ikeda
patent: 6524930 (2003-02-01), Wasshuber et al.
patent: 6562675 (2003-05-01), Watt
patent: 6569750 (2003-05-01), Kim et al.
patent: 6576558 (2003-06-01), Lin et al.
patent: 6649461 (2003-11-01), Lai et al.
patent: 6667224 (2003-12-01), Watt et al.
patent: 6717231 (2004-04-01), Kim et al.
patent: 6740944 (2004-05-01), McElheny et al.
patent: 6746936 (2004-06-01), Lee
patent: 2002/0086498 (2002-07-01), Oda et al.
patent: 2003/0111708 (2003-06-01), Hwang et al.
patent: 2003/0181004 (2003-09-01), Watt
U.S. Appl. No. 10/899,663, filed Jul. 27, 2004, Mehrotra et al.
U.S. Appl. No. 10/899,664, filed Jul. 27, 2004, Chatterjee et al.
Chatterjee Amitava
Mehrad Freidoon
Brady III W. James
Fourson George
McLarty Peter K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Method to design for or modulate the CMOS transistor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method to design for or modulate the CMOS transistor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to design for or modulate the CMOS transistor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3590522