Semiconductor memory device with built-in self test circuit...

Details Semiconductor memory device with built-in self test circuit... Semiconductor memory device with built-in self test circuit...

Filed on

2006-01-31

Date issued

2006-01-31

Examiner

Decady, Albert (Department: 2133)

Patent Class

Error detection/correction and fault detection/recovery

SubClass

Pulse or data error handling

SubSubClass

Digital logic testing

Other Related Categories

C714S731000

Type

Reexamination Certificate

Status

active

Patent number

06993696

Description

ABSTRACT:
A semiconductor memory device with a built-in self test circuit includes a semiconductor substrate, a memory cell array formed on the semiconductor substrate, an input buffer provided on the semiconductor substrate to receive externally applied data, a test circuit coupled to the memory cell array and the input buffer on the semiconductor substrate to store a program received through the input buffer to generate test data of the memory cell array according to the stored program to carry out testing of the memory cell array, and a select circuit selectively applying to the memory cell array test data applied from the test circuit and data applied from the input buffer depending upon a test operation and a normal operation.

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patent: 6223312 (2001-04-01), Nozuyama
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patent: 09-007397 (1997-01-01), None
patent: 9-62533 (1997-03-01), None
patent: 10-339765 (1998-12-01), None
patent: 11-329000 (1999-11-01), None

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