Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2006-05-02
2006-05-02
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S240000, C438S585000, C257S310000
Reexamination Certificate
active
07037862
ABSTRACT:
Embodiments in accordance with the present invention provide alternative materials, and methods of forming such materials, that are effective as dielectric layers. Such embodiments include forming metal-containing dielectric layers over a silicon-containing substrate where a metal-containing layer is first formed and that treated to form a dielectric layer. Dielectric layers formed by methods of the present invention have a dielectric constant greater than that of silicon dioxide, and can have an equivalent oxide thickness of less than 2 nanometers. Such dielectric layers are useful in the forming of a variety of semiconductor devices such as transistors, capacitors and the like where such devices and integrated circuits formed from such devices are encompassed by embodiments in accordance with the present invention.
REFERENCES:
patent: 601353 (1898-03-01), Miller
patent: 4432035 (1984-02-01), Hsieh et al.
patent: 4464701 (1984-08-01), Roberts et al.
patent: 5346600 (1994-09-01), Nieh et al.
patent: 5554564 (1996-09-01), Nishioka et al.
patent: 5566045 (1996-10-01), Summerfelt et al.
patent: 5605858 (1997-02-01), Nishioka et al.
patent: 6020024 (2000-02-01), Maiti et al.
patent: 6020243 (2000-02-01), Wallace et al.
patent: 6172385 (2001-01-01), Duncombe et al.
patent: 6184072 (2001-02-01), Kaushik et al.
patent: 6200893 (2001-03-01), Sneh
patent: 6207589 (2001-03-01), Ma et al.
patent: 6297539 (2001-10-01), Ma et al.
patent: 6300202 (2001-10-01), Hobbs et al.
patent: 6383873 (2002-05-01), Hegde et al.
patent: 6387761 (2002-05-01), Shih
patent: 6392257 (2002-05-01), Ramdani et al.
patent: 6395650 (2002-05-01), Callegari et al.
patent: 6395659 (2002-05-01), Seto et al.
patent: 6399521 (2002-06-01), Zhang et al.
patent: 6407422 (2002-06-01), Asano et al.
patent: 6436777 (2002-08-01), Ota
patent: 6444512 (2002-09-01), Madhukar et al.
patent: 6444592 (2002-09-01), Ballantine et al.
patent: 6476454 (2002-11-01), Suguro
patent: 6495890 (2002-12-01), Ono
patent: 6525967 (2003-02-01), Briner
patent: 6544875 (2003-04-01), Wilk
patent: 6573197 (2003-06-01), Callegari et al.
patent: 6664186 (2003-12-01), Callegari et al.
patent: 2001/0013629 (2001-08-01), Bai
patent: 2001/0021589 (2001-09-01), Wilk
patent: 2001/0023120 (2001-09-01), Tsunashima et al.
patent: 2001/0024868 (2001-09-01), Nagel et al.
patent: 2002/0006708 (2002-01-01), Kang et al.
patent: 2002/0047170 (2002-04-01), Ota
patent: 2002/0048910 (2002-04-01), Taylor et al.
patent: 2002/0089023 (2002-07-01), Yu et al.
patent: 2002/0094643 (2002-07-01), Solomon et al.
patent: 2002/0100946 (2002-08-01), Muller et al.
patent: 2002/0106536 (2002-08-01), Lee et al.
patent: 2002/0145168 (2002-10-01), Bojarczuk, Jr. et al.
patent: 2002/0175393 (2002-11-01), Baum
patent: 2003/0027360 (2003-02-01), Hsu
Ying Shi et al., “Tunneling Leakage Current in Ultrathin (<4nm) Nitride/Oxide Stack Dielectrics,” 3 pages (1998).
W.-H. Lee et al., “A Novel High-k Inter-Poly Dielectric (IPD), A12O3for Low Voltage/High speed Flash Memories: Erasing in msecs at 3.3V,” p. 117-118, (1997).
Xin Guo et al., “High Quality Ultra-thin (1.5 nm) TiO2/Si3N4Gate Dielectric for Deep Sub-micron CMOS technology,” 4 pages, (1999).
H.F. Luan et al., “High quality Ta2O5gate dielectrice with Tox,eq<10 Å,” 4 pages, (1999).
K.J. Hubbarda)et al., “Thermodynamic stability of binary oxides in contact with silicon,” p. 2757-2776, ( 1996).
B. Cheng et al., “The Impact of High-kGate Dielectrics and Metal Gate Electrodes on Sub-100 nm MOSFET's,” p. 1537-1544, (1999).
C.T. Liu, “Circuit Requirement and Integration Challenges of Thin Gate Dielectrics for Ultra Small MOSFETs,” 4 pages, ( 1998).
B.H. Lee et al., “Ultrathin Hafnium Oxide with Low Leakage and Excellent Reliability for Alternative Gate Dielectric Application,” 4 pages, ( 1999).
S.P. Murarka et al., “Thermal oxidation of hafnium silicide films on silicon,” 3 pages, ( 1980).
Albert Chin et al., “High Quality La2O3and Al2O3Gate Dielectric with Equivalent Oxide Thickness 5-10Å,” 2 pages, ( 2000).
D.A. Muller et al., “The electronic structure at the atomic scale of ultrathin gate oxides,” 4 pages, ( 1999).
Y. Saito et al, “High-Integrity Silicon Oxide Grown at Low-Temperature by Atomic Oxygen Generated in High-Density Krypton Plasma,” 2 pages, ( 1999).
Ahn Kie Y.
Forbes Leonard
Le Thao X.
Micro)n Technology, Inc.
Pham Long
Wells St. John P.S.
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