IC with expected data memory coupled to scan data register

Details IC with expected data memory coupled to scan data register IC with expected data memory coupled to scan data register

2006-03-14

2006-03-14

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07013416

ABSTRACT:
A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register (34), test port (38) and output control circuits (42, 46) controlled by an event qualifying module (EQM) (32). In response to a matching condition the EQM (32) may perform a variety of tests on incoming data while the integrated circuits (10, 12) continue to operate at speed. A plurality of digital bus monitors (20, 22) may be cascaded for observation and test of variable width data buses and variable width signature analysis.

REFERENCES:
patent: 4504784 (1985-03-01), Goel et al.
patent: 4929889 (1990-05-01), Seiler et al.
patent: 5084874 (1992-01-01), Whetsel, Jr.

Affiliated with

Also associated with

Rating

IC with expected data memory coupled to scan data register does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with IC with expected data memory coupled to scan data register, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and IC with expected data memory coupled to scan data register will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3579311