Method of making an electronic package

Details Method of making an electronic package Method of making an electronic package

2006-04-11

2006-04-11

Jimenez, Marc (Department: 3729)

Metal working

Method of mechanical manufacture

Electrical device making

C029S830000, C029S832000, C029S841000, C174S263000, C228S180210, C361S765000

Reexamination Certificate

active

07024764

ABSTRACT:
A method of making an electronic package. The method includes forming a semiconductor chip and an multi-layered interconnect structure. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The formed multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The method forms the electronic package to further include a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation.

REFERENCES:
patent: 5072075 (1991-12-01), Lee et al.
patent: 5121190 (1992-06-01), Hsiao et al.
patent: 5483421 (1996-01-01), Gedney et al.
patent: 5574630 (1996-11-01), Kresge et al.
patent: 5615087 (1997-03-01), Wieloch
patent: 5691041 (1997-11-01), Frankeny et al.
patent: 5798563 (1998-08-01), Feilchenfeld et al.
patent: 5838063 (1998-11-01), Sylvester
patent: 5894173 (1999-04-01), Jacobs et al.
patent: 5900675 (1999-05-01), Appelt et al.
patent: 1-307294 (1989-12-01), None
patent: 6-112271 (1994-04-01), None
patent: 9-232376 (1997-09-01), None
patent: 10-209347 (1998-08-01), None
patent: 11-87560 (1999-03-01), None
patent: 2000-022071 (2000-01-01), None
patent: 2000-024150 (2000-01-01), None
IBM Technical Disclosure Bulletin, vol. 32, No. 3B, Aug. 1989, “Multilayer Polymer Substrate for Direct Chip Attachment”.
“High Performance Carrier Technology: Materials And Fabrication”, by Light et al, 1993 International Electronics Packaging Conference, San Diego, California, Volume One.
“High Performance Carrier Technology”, by Heck et al., 1993 International Electronics Packaging Conference, San Diego, California, Volume One.
“Process Considerations in the Fabrication of Teflon Printed Circuit Boards”, by Light et al, 1994 Proceedings, 44 Electronic Components & Technology Conference, May 1994.

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