Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-05-23
2006-05-23
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07051307
ABSTRACT:
Disclosed is a method and structure that partitions an integrated circuit design by identifying logical blocks within the integrated circuit design based on size heuristics of logical macros in the design hierarchy. The invention determines whether the number of logical blocks is within a range of desired number of logical blocks and repeats the process of identifying logical blocks for different hierarchical levels of the integrated circuit design until the number of logical blocks is within the range of the desired number of logical blocks. This serves as a guide to partition the chip as opposed to a grid-like partitioning.
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Ditlow Gary S.
Dooling Daria R.
Dunham Timothy G.
Leipold William C.
Thomas Stephen D.
Gibb I.P. Law Firm LLC
International Business Machines - Corporation
Kotulak, Esq. Richard M.
Siek Vuthe
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