Thin channel MOSFET with source/drain stressors

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE27112

Reexamination Certificate

active

07112848

ABSTRACT:
Methods of manufacturing microelectronic device including, in one embodiment, forming a gate electrode over a substrate having an insulating layer interposing a bulk semiconductor portion and a thin semiconductor layer, and removing at least a portion of the thin semiconductor and insulating layers, thereby defining a pedestal comprising a portion of the thin semiconductor and insulating layers. Source/drain stressors are then formed contacting the source/drain extensions on opposing sides of the pedestal and substantially spanning a height no less than the pedestal.

REFERENCES:
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patent: 6329690 (2001-12-01), Morrett et al.
patent: 6492216 (2002-12-01), Yeo et al.
patent: 6707106 (2004-03-01), Wristers et al.
patent: 6818938 (2004-11-01), Naem
patent: 2002/0182423 (2002-12-01), Chu et al.
patent: 2004/0007715 (2004-01-01), Webb et al.
Yee-Chia Yeo, et al., “Design and Fabrication of 50-nm Thin-Body p-MOSFETs With a SiGe Heterostructure Channel”, Feb. 2002, pp. 279-286, vol. 49, No. 2, IEEE Transactions on Electron Devices, 0018-9383/02.

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