Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-07-11
2006-07-11
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C257S774000
Reexamination Certificate
active
07076750
ABSTRACT:
A method of checking a computer generated circuit layout involves selecting vias with at least an edge coincident to an edge of a metal line. Once vias are selected, based upon whether a via touches an edge of a metal line, information regarding the distance between metal lines is determined. Metal lines are resized in the vicinity of a via with an edge touching an edge of a metal line in order to effect a complete connection between the metal line and the via in a manufactured integrated circuit taking into account the information regarding the distance between metal lines. Resized metal lines do not impact metal lines adjacent to the edge that a via was touching because adjacent metal lines are resized to account for a too small separation distance if necessary.
REFERENCES:
patent: 4946764 (1990-08-01), Matsuoka et al.
patent: 5581475 (1996-12-01), Majors
patent: 5620916 (1997-04-01), Eden et al.
patent: 5640497 (1997-06-01), Woolbright
patent: 5712794 (1998-01-01), Hong
patent: 5901066 (1999-05-01), Hong
patent: 6002851 (1999-12-01), Basavaiah et al.
patent: 6038383 (2000-03-01), Young et al.
patent: 6247853 (2001-06-01), Papadopoulou et al.
patent: 6249900 (2001-06-01), Kotani et al.
patent: 6275971 (2001-08-01), Levy et al.
patent: 6340631 (2002-01-01), Chih-Po et al.
patent: 6412097 (2002-06-01), Kikuchi et al.
patent: 6425117 (2002-07-01), Pasch et al.
patent: 6526555 (2003-02-01), Teig et al.
patent: 6624056 (2003-09-01), Chandna et al.
patent: 6753611 (2004-06-01), Maeno et al.
patent: 6853743 (2005-02-01), Kotani et al.
Advanced Micro Devices , Inc.
Levin Naum
Smith Matthew
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