Design analysis workstation for analyzing integrated circuits

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000

Reexamination Certificate

active

07020853

ABSTRACT:
A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. Each image-mosaic is displayed in at least one mosaic-view as a background image that is overlaid with at least one annotation overlay. An engineer analyst creates annotation objects on the annotation overlay based on information inferred concurrently from one or more image-mosaics. Concurrent display of a plurality of image-mosaics facilitates the understanding of interrelations between components on different layers. The design analysis workstation displays a plurality of cursors in respective views of mosaic-images, the cursors having lock-step motion to facilitate comprehension of the alignment of features on different concurrently displayed image-mosaics. The design analysis workstation provides facilities for performing operations on created annotation objects including grouping, cell definition, signal carrier creation, contact creation, signal propagation, net-list generation, etc. The advantages include annotation of image-mosaics using information derived from a plurality of concurrently displayed mosaic-views to facilitate tracing of interconnected busses and an understanding of interrelations between components.

REFERENCES:
patent: 4224664 (1980-09-01), Trinchieri
patent: 4623255 (1986-11-01), Suszko
patent: 5086477 (1992-02-01), Yu et al.
patent: 5191213 (1993-03-01), Ahmed et al.
patent: 5561293 (1996-10-01), Peng et al.
patent: 5694481 (1997-12-01), Lam et al.
patent: 6288393 (2001-09-01), Phaneuf et al.
patent: 6591278 (2003-07-01), Ernst
patent: 6671424 (2003-12-01), Skoll et al.
patent: 2216589 (1997-09-01), None
patent: 2216900 (1997-09-01), None
Article: Chip Scanner System High Resolution SEM Image Capture and conversion from image to GDS-11 layout, George Lanzarotta, Raith USA, Inc., Nov. 1999.
Article “Computer-Aided Reconstruction of IC Layout from Image-Based Representation” C.C. Jong et al., Sep. 1993, Proceedings of the 5thInternational Symposium on IC Technology, Systems ADN Applications, Nanyang Technological University, Singapore.
Article: “Integrated Circuit Chip Layer Analysis”, Tan Ooi Kiang et al., Sep. 1993, Proceedings of the 5thInternational Symposium on IC Technology, System and Applications, Nanyang Technological University, Singapore.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Design analysis workstation for analyzing integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Design analysis workstation for analyzing integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Design analysis workstation for analyzing integrated circuits will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3571731

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.