Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2006-01-10
2006-01-10
Su, Thuan (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C365S189011, C365S205000, C365S240000, C365S194000
Reexamination Certificate
active
06986072
ABSTRACT:
A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.
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Funaba Seiji
Iizuka Takuo
Ikeda Hiroaki
Nishio Yoji
Shibata Kayoko
Elpida Memory Inc.
Hitachi , Ltd.
Hitachi Tohbu Semiconductor, Ltd.
Patel Anand B.
Su Thuan
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