Methods for forming vertical gate transistors providing...

Details Methods for forming vertical gate transistors providing... Methods for forming vertical gate transistors providing...

2006-03-21

2006-03-21

Chaudhari, Chandra (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S270000

Reexamination Certificate

active

07015092

ABSTRACT:
Methods and devices that provide improved isolation and alignment of gate conductors or gate contacts of vertical transistors in deep trench memory cells. A method for forming a vertical gate contact of a vertical transistor includes an oxide spacer formation process that prevents defects, such as shorts caused by voids filled with polysilicon, resulting from etching processes that are performed during fabrication of a vertical transistor, and enables formation of well-defined contact plugs for gate contacts, providing improved alignment structures.

REFERENCES:
patent: 6143599 (2000-11-01), Kim et al.
patent: 6406970 (2002-06-01), Kudelka et al.
patent: 6432774 (2002-08-01), Heo et al.
patent: 6534359 (2003-03-01), Heo et al.

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