SRAM cell design with high resistor CMOS gate structure for...

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Reexamination Certificate

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C365S063000, C365S072000, C365S148000, C365S156000, C257S364000, C257S377000, C257S380000, C257S382000, C257S393000, C257S413000, C257S536000, C257S754000

Reexamination Certificate

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06992916

ABSTRACT:
A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through a first resistor. The first memory node is coupled to an input of the second inverter through a second resistor. A pair of access transistors are respectively coupled to a pair of bit lines, a split word line and one of the memory nodes. The resistors are prepared by coating a layer of silicide material on a selective portion of the gate structure of the transistors included in the first inverter, and connecting a portion of the gate structure that is substantially void of the silicide material to the drain of the transistors included in the second inverter.

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