Superconductor device and method of manufacturing the same

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S622000, C438S618000

Reexamination Certificate

active

07026241

ABSTRACT:
A semiconductor device comprising element regions formed in a semiconductor substrate, conductor plugs embedded in an interlayer insulation film, and wiring layers connected to the plugs, wherein the plugs are arranged on a straight line orthogonal to a longitudinal direction of the wiring layer in the same pitch as the wiring layers such that the straight line and upper surfaces of the plugs are superposed each other, and when the plugs are viewed in a cross section parallel to a main surface of the substrate and a distance which is between those two edge points of each of the plugs where a split line which passes through a center of each of the plugs passes is defined as a contact diameter, the contact diameter has three or more maximum values and three or more minimum values while the split line is rotated in the cross section by 360 degrees.

REFERENCES:
patent: 5734607 (1998-03-01), Sung et al.
patent: 6160297 (2000-12-01), Shimizu et al.
patent: 6411548 (2002-06-01), Sakui et al.
patent: 6440843 (2002-08-01), Wada et al.
patent: 6444570 (2002-09-01), Shibata
K. Ueno, et al. “A Quarter-Micron Planarized Interconnection Technology with Self-Aligned Plug,” IEDM Tech. Dig., 1992, pp. 305-308.
K. Ueno, et al. “A Half-Micron Pitch Cu Interconnection Technology,” VLSI Tech., Dig., 1995, pp. 27-28.
R.F. Schnabel, et al. “Slotted Vias for Dual Damascene Interconnects in 1Gb DRAMs,” VLSI Tech. Dig., 1999, pp. 43-44.

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