Semiconductor memory

Static information storage and retrieval – Read/write circuit – Precharge

Reexamination Certificate

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C365S222000

Reexamination Certificate

active

07046564

ABSTRACT:
The invention relates to semiconductor memories, and in particular, to DRAMs with a memory subunit including a memory cell in which a data value is stored and which is adapted to be connected with a bit line to which a complementary bit line is assigned, and a precharge/equalize circuit assigned to the memory cell, the precharge/equalize circuit serving to charge, prior to the reading out of the memory cell, the bit line and the complementary bit line in the region of the memory cell to the same voltage level, and being switched off during the reading out of the memory cell. The semiconductor memory in addition has a control circuit connected with the precharge/equalize circuit for switching on and off the precharge/equalize circuit.

REFERENCES:
patent: 5339274 (1994-08-01), Dhong et al.
patent: 5805508 (1998-09-01), Tobita
patent: 6031779 (2000-02-01), Takahashi et al.
patent: 6233188 (2001-05-01), Kai
patent: 6418073 (2002-07-01), Fujita

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