Bitline of semiconductor device having stud type capping...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S396000, C438S241000

Reexamination Certificate

active

06982199

ABSTRACT:
A semiconductor device with a bitline structure has a stud type capping layer. A method of fabricating the same achieves sufficient process margins and reduces parasitic capacitance. The device may include an insulating film formed on a semiconductor substrate and having a bitline contact and a groove-shaped bitline pattern, a bitline formed on the bitline contact and on a portion of the bitline pattern and that is surrounded by the insulating film, and a bitline capping layer formed on the bitline within the bitline pattern and the insulating film that protrudes from the insulating film. A protruded portion of the bitline capping layer is wider than the width of the bitline.

REFERENCES:
patent: 6080620 (2000-06-01), Jeng
patent: 6255160 (2001-07-01), Huang
patent: 6281073 (2001-08-01), Lee
patent: 6350707 (2002-02-01), Liu et al.
patent: 6372575 (2002-04-01), Lee et al.
patent: 2002/0115256 (2002-08-01), Lee et al.
patent: 2003/0235948 (2003-12-01), Park
patent: 2001-55685 (2001-07-01), None
English language of Abstract for Korean Publication No. 2001-55685, published on Jul. 4, 2001.

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