Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-04-11
2006-04-11
Wojciechowicz, Edward (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S217000, C438S301000, C438S302000
Reexamination Certificate
active
07026218
ABSTRACT:
The present invention pertains to formation of a PMOS transistor wherein a layer of silicon or SiGe inhibits p-type dopant from entering into an underlying gate dielectric layer. The p-type dopant can be added to a gate electrode material that overlies the silicon or SiGe layer and can diffuse down toward the silicon or SiGe layer. The layer of silicon or SiGe may be formed to a thickness of about 5 to 120 nanometers and doped with a dopant, such as indium (In), for example, to deter the p-type dopant from passing through the silicon or SiGe layer. The dopant may have a peak concentration within the layer of silicon or SiGe near the interface of the silicon or SiGe layer with the underlying layer of gate dielectric material. Allowing the gate electrode to be doped with the p-type dopant (e.g., boron) facilitates forming the transistor with an associated work function having a desired value (e.g., coincident with a Fermi level of about 4.8 to about 5.6 electron volts).
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Chambers James J.
Jain Amitabh
Pacheco Rotondaro Antonio Luis
Brady III W. James
McLarty Peter K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Wojciechowicz Edward
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