Method of and apparatus for timing verification of LSI test...

Details Method of and apparatus for timing verification of LSI test... Method of and apparatus for timing verification of LSI test...

2005-06-21

2005-06-21

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06910166

ABSTRACT:
Timing verification of the LSI test data is performed as follows. In test synthesis, a script text for static timing analysis (STA) is generated together with a test circuit. The STA script text is used to perform static timing analysis. Function verification is performed between a netlist generated through the test synthesis and a timing-verified netlist based on the static timing analysis. The function-verified netlist is released to a production division, and the netlist is used to automatically generate a test pattern by an automatic test pattern generation (ATPG) tool. A netlist comprising test vectors for automatic test equipment is acquired from the generated ATPG pattern.

REFERENCES:
patent: 6401227 (2002-06-01), Yasue et al.
patent: 6453437 (2002-09-01), Kapur et al.
patent: 6473881 (2002-10-01), Lehner et al.
patent: 6832361 (2004-12-01), Cohn et al.
patent: 8-221465 (1996-08-01), None
patent: 2000-293555 (2000-10-01), None

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