Barrier in gate stack for improved gate dielectric integrity

Details Barrier in gate stack for improved gate dielectric integrity Barrier in gate stack for improved gate dielectric integrity

2005-08-16

2005-08-16

Chaudhuri, Olik (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S324000

Reexamination Certificate

active

06930363

ABSTRACT:
A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper portion of the gate polysilicon during deposition, or a silicon layer doped with nitrogen after silicon deposition. The layer is of particular utility in conjunction with CVD tungsten silicide straps.

REFERENCES:
patent: 4331709 (1982-05-01), Risch et al.
patent: 4760005 (1988-07-01), Pai
patent: 4839301 (1989-06-01), Lee
patent: 4870470 (1989-09-01), Bass et al.
patent: 4960662 (1990-10-01), Nishikawa et al.
patent: 4996081 (1991-02-01), Ellul et al.
patent: 5057449 (1991-10-01), Lowrey et al.
patent: 5073509 (1991-12-01), Lee
patent: 5094712 (1992-03-01), Becker et al.
patent: 5100826 (1992-03-01), Dennison
patent: 5177027 (1993-01-01), Lowrey et al.
patent: 5231056 (1993-07-01), Sandhu
patent: 5236865 (1993-08-01), Sandhu et al.
patent: 5240874 (1993-08-01), Roberts
patent: 5264724 (1993-11-01), Brown et al.
patent: 5266510 (1993-11-01), Lee
patent: 5272367 (1993-12-01), Dennison et al.
patent: 5306951 (1994-04-01), Lee et al.
patent: 5341016 (1994-08-01), Prall et al.
patent: 5345104 (1994-09-01), Prall et al.
patent: 5349494 (1994-09-01), Ando
patent: 5360769 (1994-11-01), Thakur et al.
patent: 5364803 (1994-11-01), Lur et al.
patent: 5376593 (1994-12-01), Sandhu et al.
patent: 5378641 (1995-01-01), Cheffings
patent: 5393683 (1995-02-01), Mathews et al.
patent: 5405791 (1995-04-01), Ahmad et al.
patent: 5407870 (1995-04-01), Okada et al.
patent: 5409853 (1995-04-01), Yu
patent: 5429972 (1995-07-01), Anjum et al.
patent: 5468987 (1995-11-01), Yamazaki et al.
patent: 5472896 (1995-12-01), Chen et al.
patent: 5527718 (1996-06-01), Seita et al.
patent: 5616948 (1997-04-01), Pfiester
patent: 5719410 (1998-02-01), Suehiro et al.
patent: 5773325 (1998-06-01), Teramoto
patent: 5776823 (1998-07-01), Agnello et al.
patent: 5861340 (1999-01-01), Bai et al.
patent: 5877095 (1999-03-01), Tamura et al.
patent: 5940725 (1999-08-01), Hunter et al.
patent: 5977561 (1999-11-01), Wu
patent: 6015997 (2000-01-01), Hu et al.
patent: 6020260 (2000-02-01), Gardner
patent: 6037639 (2000-03-01), Ahmad
patent: 6294820 (2001-09-01), Lucas et al.
patent: 6310300 (2001-10-01), Cooney et al.
patent: 6373114 (2002-04-01), Jeng et al.
patent: 6380055 (2002-04-01), Gardner et al.
patent: 6562730 (2003-05-01), Jeng
patent: 0 682 359 (1995-11-01), None
Shimizu et al., “Impact of surface proximity Gettering and Nitrided Oxide Side-Wall Spacer by Nitrogen Implantation on Sub-Quarter Micron CMOS LDD FETs,”IEDM, vol. 95, pp. 859-862 (1995).
Silicon Processing for the VLSI Era—vol. 1—Processing Technology, pp. 191-194 (1986).

Affiliated with

Also associated with

Rating

Barrier in gate stack for improved gate dielectric integrity does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Barrier in gate stack for improved gate dielectric integrity, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Barrier in gate stack for improved gate dielectric integrity will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3513082