Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-11-15
2005-11-15
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S268000, C438S212000, C438S157000
Reexamination Certificate
active
06964903
ABSTRACT:
A method provides a structure that includes dual-gated metal-oxide semiconducting field effect transistor (MOSFET). The dual-gated MOSFET can be fabricated according to current CMOS processing techniques. The method includes forming a body region of the dual-gated MOSFET as a fully depleted structure. The structure includes two gates which are positioned on opposite sides of the opposing sides of the body region. Further, the structure operates as one device where the threshold voltage of one gate depends on the bias of the other gate. Thus, the structure yields a small signal component in analog circuit applications which depends on the product of the signals applied to the gates, and not simply one which depends on the sum of the two signals.
REFERENCES:
patent: 4287083 (1981-09-01), McDowell et al.
patent: 4605909 (1986-08-01), Tsironis
patent: 4680853 (1987-07-01), Lidow et al.
patent: 5006909 (1991-04-01), Kosa
patent: 5057896 (1991-10-01), Gotou
patent: 5308782 (1994-05-01), Mazure et al.
patent: 5391895 (1995-02-01), Dreifus
patent: 5585288 (1996-12-01), Davis et al.
patent: 5661424 (1997-08-01), Tang
patent: 5675164 (1997-10-01), Brunner et al.
patent: 5804848 (1998-09-01), Mukai
patent: 5998834 (1999-12-01), Williams et al.
patent: 6060746 (2000-05-01), Bertin et al.
patent: 6097065 (2000-08-01), Forbes et al.
patent: 6150687 (2000-11-01), Noble et al.
patent: 6320222 (2001-11-01), Forbes et al.
patent: 60-116163 (1985-06-01), None
patent: 4370978 (1992-12-01), None
GaAsIC Symposium, IEEE Gallium Arsenide Integrated Cisuit Symposium, 19th Annual Technical Digest, Anaheim, California, pp. 1-290, (Oct. 12-15, 1997).
Asai, S., et al., “The GaAs Dual-Gate Fet With Low Noise And Wide Dynamic Range”,Technical Digest, International Electron Devices Meeting, pp. 64-67, (Dec. 1973).
Colinge, J.P., “Reduction of Kink Effect in Thin-Film SOI MOSFET's”,IEEE Electron Device Letters, 9 (2), pp. 97-99, (1988).
Denton, J.P., et al., “Fully Depleted Dual-Gated Thin-Film SOI P-MOSFET's Fabricated in SOI Islands with an Isolated Buried Polysilicon Backgate”,IEEE Electron Device Letters, 17 (11), pp. 509-511, (Nov.1996).
Mizuno, T., et al., “High Speed and Highly Reliable Trench MOSFET with Dual-Gate”, 1988Symposium on VLSI Technolgy, Digest of Technical Papers, pp. 23-24, 991, (1988).
Nishinohara, K., et al., “Effects of Microscopic Fluctuations in Dopant Distributions on MOSFET Threshold Voltage”,IEEE Transactions on Electron Devices, 39 (3), pp. 634-639, (Mar. 1992).
Stolk, P.A., et al., “The Effect of Statistical Dopant Fluctuations on MOS Device Performance”,IEEE, pp. 23.4.1-23.4.4, (1996).
Sze, S.M.,In: Physics of Semiconductor Devices, Second Edition, Wiley-Interscience Publications, John Wiley & Sons, New York, p. 362-279, 433-338, (1981).
Takeuchi, K., et al., “Channel Engineering for the Reduction of Random-Dopant-Placement-Induced Theshold Voltage Fluctuations”,IEEE, pp. 33.6.1-33.6.4, (1997).
Taur, Y., et al., “CMOS Devices below 0.1 micrometer: How High Will Performance Go?”,IEEE, pp. 9.1.1-9.1.4, (1997).
Wong, H.S., et al., “Self-Aligned (Top and Bottom) Double-Gate MOSFET with a 25 nm Thick Silicon Channel”,IEEE, pp. 16.6.1-16.6.4, (1997).
Wong, H.S., et al., “Three-Dimensional “Atomistic” Simulation of Discrete Random Dopant Distribution Effects in Sub-0.1 micrometer MOSFET's”,IEEE, pp. 29.2.1-29.2.4, (1993).
Schwegman Lundberg Woessner & Kluth P.A.
Trinh Michael
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