Tightly spaced gate formation through damascene process

Details Tightly spaced gate formation through damascene process Tightly spaced gate formation through damascene process

2005-08-23

2005-08-23

Sarkar, Asok Kumar (Department: 2891)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S257000, C438S637000

Reexamination Certificate

active

06933219

ABSTRACT:
The invention includes an apparatus and a method of manufacturing such apparatus using a damascene process. The method includes the step of patterning a layer disposed over a substrate to include a line and space pattern. The line and space pattern in the layer includes at least one space comprising a width dimension of a feature to be formed. The feature may be, e.g., a wordline(s)/gate electrode(s). Additionally, the sidewalls of the feature, e.g., the wordline(s)/gate electrode(s) include relatively smooth surfaces.

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Huang et al., “Very Low Defects and High Performance Ge—On—Insulator p—MOSFETs with Al203 Gate Dielectrics”, 2003 Symposium on VLSI Technology Digest of technical papers, p 119-120 (Jun. 10-12, 2003).

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