Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-11-08
2005-11-08
Tran, Minh Wan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S903000, C365S185080
Reexamination Certificate
active
06963103
ABSTRACT:
Structures and methods are provided for SRAM cells having a novel, non-volatile floating gate transistor, e.g. a non-volatile memory component, within the cell which can be programmed to provide the SRAM cell with a definitive asymmetry so that the cell always starts in a particular state. The SRAM cells include a pair of cross coupled transistors. At least one of the cross coupled transistors includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator.
REFERENCES:
patent: 4295150 (1981-10-01), Adam
patent: 4412902 (1983-11-01), Michikami et al.
patent: 4757360 (1988-07-01), Faraone
patent: 4780424 (1988-10-01), Holler et al.
patent: 5042011 (1991-08-01), Casper et al.
patent: 5071782 (1991-12-01), Mori
patent: 5073519 (1991-12-01), Rodder
patent: 5280205 (1994-01-01), Green et al.
patent: 5350738 (1994-09-01), Hase et al.
patent: 5399516 (1995-03-01), Bergendahl et al.
patent: 5418389 (1995-05-01), Watanabe
patent: 5497494 (1996-03-01), Combs et al.
patent: 5498558 (1996-03-01), Kapoor
patent: 5508544 (1996-04-01), Shah
patent: 5600592 (1997-02-01), Atsumi et al.
patent: 5618575 (1997-04-01), Peter
patent: 5619642 (1997-04-01), Nielsen et al.
patent: 5627785 (1997-05-01), Gilliam et al.
patent: 5677867 (1997-10-01), Hazani
patent: 5691230 (1997-11-01), Forbes
patent: 5801401 (1998-09-01), Forbes
patent: 5852306 (1998-12-01), Forbes
patent: 5880991 (1999-03-01), Hsu et al.
patent: 5923056 (1999-07-01), Lee et al.
patent: 5936274 (1999-08-01), Forbes et al.
patent: 5952692 (1999-09-01), Nakazato et al.
patent: 5981350 (1999-11-01), Geusic et al.
patent: 5986935 (1999-11-01), Iyama et al.
patent: 5991225 (1999-11-01), Forbes et al.
patent: 6025228 (2000-02-01), Ibok et al.
patent: 6025627 (2000-02-01), Forbes et al.
patent: 6031263 (2000-02-01), Forbes et al.
patent: 6069380 (2000-05-01), Chou et al.
patent: 6069816 (2000-05-01), Nishimura
patent: 6124729 (2000-09-01), Noble et al.
patent: 6134175 (2000-10-01), Forbes et al.
patent: 6135175 (2000-10-01), Gaudreault et al.
patent: 6141238 (2000-10-01), Forbes et al.
patent: 6141248 (2000-10-01), Forbes et al.
patent: 6143636 (2000-11-01), Forbes et al.
patent: 6163049 (2000-12-01), Bui
patent: 6169306 (2001-01-01), Gardner et al.
patent: 6208164 (2001-03-01), Noble et al.
patent: 6210999 (2001-04-01), Gardner et al.
patent: 6229175 (2001-05-01), Uchida
patent: 6238976 (2001-05-01), Noble et al.
patent: 6246606 (2001-06-01), Forbes et al.
patent: 6249020 (2001-06-01), Forbes et al.
patent: 6249460 (2001-06-01), Forbes et al.
patent: 6307775 (2001-10-01), Forbes et al.
patent: 6323844 (2001-11-01), Yeh et al.
patent: 6351411 (2002-02-01), Forbes et al.
patent: 6424001 (2002-07-01), Forbes et al.
patent: 6461931 (2002-10-01), Eldridge
patent: 6475857 (2002-11-01), Kim et al.
patent: 6541280 (2003-04-01), Kaushik et al.
patent: 6586797 (2003-07-01), Forbes et al.
patent: 2001/0013621 (2001-08-01), Nakazato
patent: 2002/0106536 (2002-08-01), Jongho et al.
patent: 2002/0137250 (2002-09-01), Nguyen et al.
Afanas'EV, V, et al., “Electron energy barriers between (100)Si and ultrathin stacks of SiO2, AI203, and ZrO3 and ZrO2 insulators”,Applied Physics Letters, 78(20), pp. 3073-3075.
Arya, S., et al., “Conduction Properties of Thin Al2O3 Films”,Thin Solid Films, 91, (1982), pp. 363-374.
Dipert, Brian, et al., “Flash Memory Goes Mainstream”,IEEE Spectrum, 30, (Oct. 1993), pp. 48-52.
Eierdal, L., et al., “Interaction of oxygen with Ni(110) studied by scanning tunneling microscopy”,Surface Science, 312, (1994), pp. 31-53.
Eldridge, J., et al., “Analysis of Ultrathin Oxide Growth on Indium”,Thin Solid Films, 12, (1972), pp. 447-451.
Eldridge, J. M., et al., “Growth of Thin PbO Layers on Lead Films”,Surface Science, 40, (1973), pp. 512-530.
Eldridge, J., et al., “Measurement of Tunnel Current Density in a Metal-Oxide-Metal System as a Function of Oxide Thickness”,Proc. 12th Intern. Conf. on Low Temperature Physics, (1971), pp. 427-428.
Greiner, J., “Josephson Tunneling Barriers by rf Sputter Etching in an Oxygen Plasma”,Journal of Applied Physics, vol. 42, No. 12, (Nov. 1971), pp. 5151-5155.
Greiner, J., “Oxidation of lead films by rf sputter etching in an oxygen plasma”,Journal of Applied Physics, 45(1), (1974), pp. 32-37.
Grimbolt, J., “I. Interaction of Al Films with O2 at Low Pressures”,Journal of the Electrochemical Society, 129(10), (1982), pp. 2366-2368.
Grimbolt, J., “II. Oxidation of Al Films”,Journal of Electrochem Soc.: Solid-State Science and Technology, (1982), pp. 2369-2372.
Gundlach, K., et al., “Logarithmic Conductivity of Al-Al2O3-Al Tunneling Junctions Produced by Plasma and by Thermal Oxidation”,Surface Science, 27, (1971), pp. 125-141.
Guo, X., “High Quality Ultra-thin (1.5 nm) TiO2/Si3N4 Gate Dielectric for Deep Sub-micron CMOS Technology”,IEDM Technical Digest, (1999), pp. 137-140.
Hodges, D. A., et al.,Analysis and Design of Digital Integrated Circuits, McGraw-Hill Book Company, 2nd Edition, (1988), 394-396.
Hurych, Z., “Influence on Non-Uniform Thickness of Dielectric Layers on Capacitance and Tunnel Currents”,Solid-State Electronics, vol. 9, (1966), pp. 967-979.
Itokawa, H, “Determination of Bandgap and Energy Band Alignment for High-Dielectric-Constant Gate Insulators Using High-Resolution X-ray Photoelectron Spectroscopy”,Extended Abstracts of the 1999 International Conference on Solid State Devices and MAterials, (1999), pp. 158-159.
Kim, H., “Leakage current and electrical breakdown in metal-organic chemical vapor deposited TiO2 dielectrics on silicon substrates”,Applied Phys. Lett., 69(65), pp. 3860-3862.
Kubaschewski, O., et al.,Oxidation of Metals and Alloys, Second Edition, Butterworths, London, (1962), pp. 1-3, 5,6, 8-12, 24, 36-39.
Kubaschewski, O., et al.,Oxidation of Metals and Alloys, Butterworths, London, (1962), pp. 53-63.
Kukli, K., “Development of Dielectric Properties of Niobium Oxide, Tantalum Oxide, and Aluminum Oxide Based Nanolayered Materials”,Journal of the Electrochemical Society, 148(2), (2001), pp. F35-F41.
Kwo, J., “Properties of high k gate dielectrics Gd2O3 and Y2O3 for Si”,Journal of Applied Physics, 89(7), pp. 3920-3927.
Luan, H., et al., “High Technology Ta2O5 Gate Dielectrics with Tox,eq<10A”,IEDM, (1999), pp. 141-144.
Ma, Y., “Zirconium Oxide Based Gate Dielectrics with equivalents Oxide Thinkness of LEss Than 1.0 nm and Performance of Submicron MOSFET using a Nitride Gate Replacement Process”,IEDM—Technical Digest, (1999), pp. 149-152.
Marshalek, R., et al., “Photoresponse Characteristics of Thin-Film Nickel-Nickel Oxide-Nickel Tunneling Junctions”,IEEE Journal of Quantum Electronics, QE-19(4), (1983), pp. 749-754.
Masuoka, F., et al., “A 256K Flash EEPROM using Triple Polysilicon Technology”,IEEE International Solid-State Circuits Conference, Digest of Technical Papers, (1985), pp. 168-169.
Masuoka, F., et al., “A New Flash EEPROM Cell using Triple Polysilicon Technology”,International Electron Devices Meeting, Technical Digest, San Francisco, CA, (1984), pp. 464-467.
Mori, S., et al., “Reliable CVD Inter-Poly Dielectrics for Advanced E&EEPROM”,Symposium on VSLI Technology, Digest of Technical Papers, (1985), pp.16-17.
Muller, H., “Electrical and Optical Properties of Sputtered In2O3 Films”,Physica Status Solidi, 27(2), (1968), pp. 723-731.
Pashley, R., et al., “Flash Memories: the best of two worlds”,IEEE Spectrum, (1989), pp. 30-33.
Pollack, S., et al., “Tunneling Through Gaseous Oxidized Films of Al2O3”,Transactions of
Schwegman Lundberg Woessner & Kluth P.A.
Tran Minh Wan
LandOfFree
SRAM cells with repressed floating gate memory, low tunnel... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with SRAM cells with repressed floating gate memory, low tunnel..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SRAM cells with repressed floating gate memory, low tunnel... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3507925