Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-08-02
2005-08-02
Chaudhari, Chandra (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S256000
Reexamination Certificate
active
06924192
ABSTRACT:
A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in the top ends of contact plugs (83b) electrically connected to ones of source/drain regions (59). Lower electrodes (70) of capacitors (73) are formed in contact with the conductive barrier layers (82) of the contact plugs (83b) and then dielectric films (71) and upper electrodes (72) of the capacitors (73) are sequentially formed. In the logic region, contact plugs (25) are formed in an upper layer so that they are in contact respectively with contact plugs (33) electrically connected to source/drain regions (9).
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patent: 6528366 (2003-03-01), Tu et al.
patent: 6656786 (2003-12-01), Chiang et al.
patent: 6797557 (2004-09-01), Chiang
patent: 10-150161 (1998-06-01), None
patent: 2001-267516 (2001-09-01), None
patent: 2001-284541 (2001-10-01), None
Chaudhari Chandra
Renesas Technology Corp.
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