Process of fabricating a chip structure

Details Process of fabricating a chip structure Process of fabricating a chip structure

2005-08-30

2005-08-30

Chambliss, Alonzo (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S614000, C438S622000, C029S829000, C029S874000

Reexamination Certificate

active

06936531

ABSTRACT:
A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

REFERENCES:
patent: 5357403 (1994-10-01), Haller et al.
patent: 5635767 (1997-06-01), Wenzel et al.
patent: 6303423 (2001-10-01), Lin
patent: 6756295 (2004-06-01), Lin et al.
patent: 6818540 (2004-11-01), Saran et al.

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