Process for a flash memory with high breakdown resistance...

Details Process for a flash memory with high breakdown resistance... Process for a flash memory with high breakdown resistance...

2005-06-21

2005-06-21

Chen, Jack (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S266000

Reexamination Certificate

active

06908814

ABSTRACT:
A selfaligned process for a flash memory comprises applying a solution with a high etch selectivity to etch the sidewall of the tungsten silicide in the gate structure of the flash memory during a clean process before forming a spacer for the gate structure. This process prevents the gate structure from degradation caused by thermal stress.

REFERENCES:
patent: 5210047 (1993-05-01), Woo et al.
patent: 6143611 (2000-11-01), Gilton et al.
patent: 6448140 (2002-09-01), Liaw
patent: 6740550 (2004-05-01), Choi et al.
patent: 2003/0181007 (2003-09-01), Huang et al.

Affiliated with

Also associated with

Rating

Process for a flash memory with high breakdown resistance... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for a flash memory with high breakdown resistance..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for a flash memory with high breakdown resistance... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3495928