Semiconductor fabrication process with asymmetrical...

Details Semiconductor fabrication process with asymmetrical... Semiconductor fabrication process with asymmetrical...

2005-11-22

2005-11-22

Thomas, Tom (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S267000, C438S283000, C438S303000, C438S596000

Reexamination Certificate

active

06967143

ABSTRACT:
A semiconductor process and resulting transistor includes forming conductive extension spacers (146, 150) on either side of a gate electrode (116). Conductive extensions (146, 150) and gate electrode116are independently doped such that each of the structures may be n-type or p-type. Source/drain regions (156) are implanted laterally disposed on either side of the spacers (146, 150). Spacers (146, 150) may be independently doped by using a first angled implant (132) to dope first extension spacer (146) and a second angled implant (140) to dope second spacer (150). In one embodiment, the use of differently doped extension spacers (146, 150) eliminates the need for threshold adjustment channel implants.

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