Methods of forming memory cell arrays

Details Methods of forming memory cell arrays Methods of forming memory cell arrays

2005-10-25

2005-10-25

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06958268

ABSTRACT:
The invention includes a method of forming an array of memory cells. A series of capacitor constructions is formed, with the individual capacitor constructions having storage nodes. The capacitor constructions are defined to include a first set of capacitor constructions and a second set of capacitor constructions. A series of electrically conductive transistor gates are formed over the capacitor constructions and in electrical connection with the capacitor constructions. The transistor gates are defined to include a first set that is in electrical connection with the storage nodes of the first set of capacitor constructions, and a second set that is in electrical connection with the storage nodes of the second set of capacitor constructions. A first conductive line is formed over the transistor gates and in electrical connection with the first set of transistor gates, and a second conductive line is formed over the first conductive line and in electrical connection with the second set of transistor gates. The invention also includes an array of memory cells.

REFERENCES:
patent: 5055898 (1991-10-01), Beilstein, Jr. et al.
patent: 5316962 (1994-05-01), Matsuo et al.
patent: 6144055 (2000-11-01), Takenaka
patent: 6423596 (2002-07-01), McKee

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