Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-02-01
2005-02-01
Chen, Jack (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S266000, C438S267000
Reexamination Certificate
active
06849500
ABSTRACT:
A method, for manufacturing a nonvolatile memory device, includes: forming a first insulating layer above a semiconductor layer; forming a first conductive layer above the first insulating layer: forming a stopper layer above the first conductive layer; patterning the stopper layer and the first conductive layer; forming an ONO film made of a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer above the semiconductor layer and on both side surfaces of the first conductive layer; forming a second conductive layer above the ONO film; applying anisotropic etching to the second conductive layer, and thereby forming a side wall-like control gate aside each of both side surfaces of the first conductive layer, the ONO film being interposed therebetween; forming an impurity layer to be a source region or a drain region inside of the semiconductor layer; forming a second insulating layer over an entire surface; polishing the second insulating layer so as to expose the stopper layer; removing the stopper layer; forming, on the entire surface, a third conductive layer made of a laminate film of a titanium layer and a titanium nitride layer; patterning the third conductive layer and thereby forming a word line; and patterning the first conductive layer and thereby forming a word gate.
REFERENCES:
patent: 5408115 (1995-04-01), Chang
patent: 5422504 (1995-06-01), Chang et al.
patent: 5494838 (1996-02-01), Chang et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 6177318 (2001-01-01), Ogura et al.
patent: 6191441 (2001-02-01), Aoki et al.
patent: 6248633 (2001-06-01), Ogura et al.
patent: 6255166 (2001-07-01), Ogura et al.
patent: 6413821 (2002-07-01), Ebina et al.
patent: 6518124 (2003-02-01), Ebina et al.
patent: 6627491 (2003-09-01), Ebina et al.
patent: 20020100929 (2002-08-01), Ebina et al.
patent: 20020127805 (2002-09-01), Ebina et al.
patent: 20030054610 (2003-03-01), Ebina et al.
patent: 20030057505 (2003-03-01), Ebina et al.
patent: 20030058705 (2003-03-01), Ebina et al.
patent: 20030060011 (2003-03-01), Ebina et al.
patent: 01-239956 (1989-09-01), None
patent: 7-161851 (1995-06-01), None
patent: 2978477 (1999-09-01), None
patent: 2001-007046 (2001-01-01), None
patent: 2001-148434 (2001-05-01), None
patent: 2001-156188 (2001-06-01), None
Chen, et al., “A Novel Flash Memory Device with S Plit Gate Source Side Injection and ONO Charge Storage Stack (SPIN),” 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 63-64.
Chang, et al., “A New SONOS Memory Using Source-Side Injection for Programming,” IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, pp. 253-255.
Hayashi, et al., “Twin MONOS Cell with Dual Control Gates,” 2000 Symposium on VLSI Technology Digest of Technical Papers (2 pages).
Communication from Japanese Patent Office re: counterpart application.
Kato Aiko
Shibata Takumi
Chen Jack
Harness & Dickey & Pierce P.L.C.
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