Method for semiconductor gate line dimension reduction

Details Method for semiconductor gate line dimension reduction Method for semiconductor gate line dimension reduction

2005-02-01

2005-02-01

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S595000, C438S636000

Reexamination Certificate

active

06849530

ABSTRACT:
To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

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