Methods for fabricating semiconductor devices

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S256000, C438S396000, C438S399000, C438S638000, C438S640000, C438S672000, C438S673000, C438S704000

Reexamination Certificate

active

06852592

ABSTRACT:
A method for fabricating a semiconductor device includes forming a plurality of first plugs contacted to a substrate by passing through a first inter-layer insulation layer; forming a second inter-layer insulation layer on the first plugs; forming a conductive pattern contacted to a group of the first plugs by etching selectively the second inter-layer insulation layer; and forming a contact hole exposing a surface of the first plug that is not contacted to the conductive pattern by etching selectively the second insulation layer with use of a dry-type and wet-type etch process, wherein an attack barrier layer is formed on between the first inter-layer insulation layer and the second inter-layer insulation layer to thereby prevent an incidence of attack to the first interlayer insulation layer contacted to the first plug during the wet-type etch process for forming the contact hole.

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patent: 6413816 (2002-07-01), Kim
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patent: 20030122174 (2003-07-01), Fukuzumi
Wolf, Ph.D., Stanley, Richard Tauber, Ph.D., “Multi-Level Interconnect Technology for VLSI and ULSI,” Semiconductor Processing for the VLSI Era—vol. 2: Process Integration, Lattice Press, 1986, pp. 194-199.

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