Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Metastable state prevention
Reexamination Certificate
2005-02-08
2005-02-08
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Metastable state prevention
C326S021000, C326S026000, C327S198000, C327S199000, C327S022000, C327S023000
Reexamination Certificate
active
06853218
ABSTRACT:
An apparatus comprising a first arbiter cell, a second arbiter cell and a selection device. The first arbiter cell may be configured to lock if one or more requests are not resolved within a first predetermined time period. The second arbiter cell may be configured to dominate if the first arbiter cell enters a metastable state. The selection device may be configured to provide arbitration between the first and second arbiter cells within a second predetermined time period.
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Cypress Semiconductor Corp.
Maiorana PC Christopher P.
Tan Vibol
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