Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-08-02
2005-08-02
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06925590
ABSTRACT:
A scan interface for an integrated circuit includes a scan clock and a scan mode signal. The scan mode signal is indicative of whether or not scan is active, and may be used by dedicated scan circuitry in integrated circuit. Such circuitry may be inactive if the scan mode indicates that scan is inactive, and active if the scan mode indicates that scan is active. For example, the scan circuitry may not toggle is scan is inactive. The scan circuitry may present a reduced load to functional circuitry if scan is inactive. In some embodiments, static and dynamic scan circuits are included for use with static and dynamic logic circuits, respectively.
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Broadcom Corporation
Garlick Harrison & Markison LLP
Kerveros James C
Lamarre Guy J.
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