Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-02-15
2005-02-15
Thai, Luan (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S589000, C438S173000, C438S268000
Reexamination Certificate
active
06855604
ABSTRACT:
The present invention relates to a method for fabricating a metal-oxide semiconductor (MOS) transistor having a gate electrode with a stack structure of a polysilicon layer, a tungsten nitride barrier layer and a tungsten layer. According to the present invention, a depth from a lastly deposited nitride layer to a bottom surface of a trench is shallower, and thereby decreasing incidences of a void generation. Also, the present invention provides an advantage of an elaborate manipulation of well and channel dopings by performing ion-implantations with two different approaches. Furthermore, it is possible to enhance device characteristics by decreasing gate induced drain leakage (GIDL) currents and improving a capability of driving currents. This decrease of the GIDL currents and the improved driving current capability are obtained by forming the gate oxide layer with different thicknesses.
REFERENCES:
patent: 6689664 (2004-02-01), Park
Udo Schwalke, et al.; “Dual-Workfunction Gate Engineering in a Corner Parasitics-Free Shallow-Trench-Isolation Complementary-Metal-Oxide-Semiconductor Technology”; Jpn. J. Appl. Phys. vol. 38; 1999; pp. 2232-2237.
Hynix / Semiconductor Inc.
Piper Rudnick LLP
Thai Luan
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