Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Patent
1995-12-14
1997-04-22
Dinh, Son T.
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
365149, 365203, 327589, G11C 700
Patent
active
056234465
ABSTRACT:
A DRAM operable in a precharge cycle and an activation cycle, includes word lines, bit lines in which a first bit line and a second bit line are included, memory cells located between the first bit line and the second bit line, a first node and a second node through which data in the memory cell is transferred, a transfer gate to connect the first bit line to the first node and the second bit line to the second node, a sense amplifier located between the first node and the second node, an equalizer for equalizing the first node and the second node located between the first node and the second node, a voltage booster for boosting the control signal for the transfer gate and the equalizer. In the DRAM, the control signals for the transmisiion gate and the equalizer are set at V.sub.CC during the precharge cycle, and boosted above V.sub.CC in the activation cycle after the precharge cycle, and the control signal for the transfer gate is changed to V.sub.CC and the control signal for the equalizer is changed to the ground potential V.sub.SS in synchronization with a selection of the word line.
REFERENCES:
patent: 4382194 (1983-05-01), Nakano et al.
patent: 5175448 (1992-12-01), Fujii
patent: 5243574 (1993-09-01), Ikeda
patent: 5291450 (1994-03-01), Fujiwara et al.
patent: 5355343 (1994-10-01), Shu et al.
Hisada Toshiki
Koinuma Hiroyuki
Dinh Son T.
Kabushiki Kaisha Toshiba
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