Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-06-28
2005-06-28
Deo, Duy-Vu N. (Department: 1765)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S634000, C438S635000, C438S692000, C438S717000
Reexamination Certificate
active
06911389
ABSTRACT:
Methods are disclosed for forming vias, trenches, and interconnects through diffusion barrier, etch-stop, and dielectric materials for interconnection of electrical devices in dual damascene structures of a semiconductor device. A buried via mask at the etch-stop level provides openings with two or more adjacent via misalignment error regions merged into rectangular windows aligned orthogonal to a long axis of the underlying conductive features of a first metal level. The rectangular windows used together with openings in a hard mask form via portions, and the openings in the hard mask provide trench portions. Via and trench portions coincide during trench or via etch, as well as during hard mask or etch-stop layer etch together forming an interconnect cavity, which may then be filled with a conductive material to provide a conductive interconnect between the conductive feature of the first metal level and a second metal level.
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Brennan Kenneth D.
Gillespie Paul
Brady III W. James
Deo Duy-Vu N.
Garner Jacqueline J.
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