Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-05-03
2005-05-03
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S315000, C257S316000, C257S319000, C257S320000
Reexamination Certificate
active
06888190
ABSTRACT:
A low-voltage nonvolatile memory array includes an N type semiconductor substrate having a memory region. A deep P well is formed in the semiconductor substrate. A cell N well is located within the memory region in the semiconductor substrate. The cell N well is situated above the deep ion well. A shallow P well serving as a buried bit line is doped within the cell ion well. The shallow P well is isolated by an STI layer, wherein the STI layer has a thickness greater than a well depth of the shallow ion well. At least one memory transistor with a stacked gate, a source, and a drain is formed on the shallow ion well. The source of the memory transistor is electrically coupled to the cell N well to induce a capacitor between the cell N well and the deep P well during a read operation, thereby avoiding read current bounce or potential power crash. A bit line overlies the memory transistor and is electrically connected to the drain of the memory transistor via a bit line contact plug short-circuiting the drain of the memory transistor and the shallow P well.
REFERENCES:
patent: 6696724 (2004-02-01), Verhaar
patent: 20030198087 (2003-10-01), Kinsey et al.
patent: 20040079988 (2004-04-01), Harari
Hsu Ching-Hsiang
Shen Shih-Jye
Yang Ching-Sung
e-Memory Technology, Inc.
Fenty Jesse A.
Hsu Winston
Jackson Jerome
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