Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-05-03
2005-05-03
Lee, HsienMing (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S230000, C438S570000, C438S571000, C438S576000, C438S581000
Reexamination Certificate
active
06887747
ABSTRACT:
There is disclosed a semiconductor device in which a device isolating insulating film is formed in a periphery of a device region of a semiconductor silicon substrate device region. A side wall insulating film formed of a silicon nitride film is formed to cover the periphery of a channel region on the silicon substrate. A Ta2O5film, and a metal gate electrode are formed inside a trench whose side wall is formed of the side wall insulating film. An interlayer insulating film is formed on the device isolating insulating film. A Schottky source/drain formed of silicide is formed on the silicon substrate in a bottom portion of the trench whose side wall is formed of the side wall insulating film and interlayer insulating film. A source/drain electrode is formed on the Schottky source/drain.
REFERENCES:
patent: 4434013 (1984-02-01), Bol
patent: 4485550 (1984-12-01), Koeneke et al.
patent: 4586063 (1986-04-01), Nakamura et al.
patent: 4769686 (1988-09-01), Horiuchi et al.
patent: 4783688 (1988-11-01), Shannon
patent: 5159416 (1992-10-01), Kudoh
patent: 5512502 (1996-04-01), Ootsuka et al.
patent: 6081007 (2000-06-01), Matsuoka
patent: 6204539 (2001-03-01), Oyamatsu
patent: 6303479 (2001-10-01), Snyder
patent: 1991-0006249 (1984-12-01), None
patent: WO 8601641 (1986-03-01), None
Atsushi Yagishita, et al., “Semiconductor Device And Method Of Manufacturing The Same”, US patent application Ser. No. 09/105,960, Filed: Jun. 29, 1998.
Jakub Kedzierski et al., “Complementary Silicide Source/Drain Thin-Body MOSFETs For The 20NM Gate Length Regime”, Department of Electrical Engineering and Computer Sciences, University of California, IEDM Tech. Dig., pp. 57-60, Apr. 2000.
S.A. Rishton, New Complimentary Metal-Oxide Semiconductor Technology With Self-Aligned Schottky Source/Drain And Low-Resistance T Gates, IBM Research Division, J. Vac. Sci. Technology B 15(6), pp. 2795-2798, Nov./Dec. 1997.
A. Chatterjee et al., “Sub-100nm Gate Length Metal Gate NMOS Transistors Fabricated by a Replacement Gate Process”, IEDM Tech. Dig., (1997), pp. 821-824.
A. Yagishita et al., “High Performance Metal Gate MOSFETs Fabricated by CMP for 0.1μm Regime”, IEDM Tech. Dig., (1998), pp. 785-788.
B. Cheng et al., “The Impact of High-κ Gate Dielectrics and Metal Gate Electrodes on Sub-100 nm MOSFET's”, IEEE Transactions on Electron Devices, Vo. 46, No. 7, Jul. 1999, pp. 1537-1544.
English-language translation of Office Action dated May 17, 2004 from the Korean Patent Office in Korean Application No. 10-2001-0041173.
Matsuo Kouji
Yagishita Atsushi
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Lee Hsien-Ming
LandOfFree
Method of forming a MISFET having a schottky junctioned... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a MISFET having a schottky junctioned..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a MISFET having a schottky junctioned... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3454343