DRAM with segmental cell arrays and method of accessing same

Details DRAM with segmental cell arrays and method of accessing same DRAM with segmental cell arrays and method of accessing same

2005-03-01

2005-03-01

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S203000, C365S196000, C365S204000, C365S230050

Reexamination Certificate

active

06862244

ABSTRACT:
In a semiconductor memory device having a plurality of memory cells grouped in memory banks, each memory bank having a plurality of memory blocks accessible by a common row address, a method of reading from or writing to the plurality of memory blocks, comprising the steps of detecting successive read or write operations of different blocks, prefetching the address of the next block to be read or written during the first of the successive read or write operations; and withholding a precharge of the memory bank having the successively read or written memory blocks after the first of the successive read or write operations until completion of the successive read or write operations. A semiconductor memory device is also provided having a circuit for inhibiting the activation of the precharge signal at the end of a first memory access operation when successive memory access operations are to be performed with the first memory access operation at a first row address and a first memory block and the next memory access operation at the same first row address and a second memory block having a block address different from the first memory block.

REFERENCES:
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patent: 6084806 (2000-07-01), Sugibayashi
Yasuharu Sato. et al. “Fast Cycle RAM (FCRAM): a 10-ns Random Row Access, Pipe-lined Operating DRAM,” 1998 Symposium on VLSI Circuits Digest of Technical Papers. pp. 22-25.

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